1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a step of patterning one layer using a plurality of reticles.
2. Description of the Related Art
With recent miniaturization of semiconductor devices, formation of miniaturized wirings and miniaturized pitches are required. Consequently, a multiple exposure process using a plurality of reticles (exposure masks) is introduced for patterning of one layer.
The multiple exposure process comprises the steps of, first, forming a layer to be patterned on or above a semiconductor substrate to form a resist film thereon by coating. Then, a first sheet of the reticle is aligned to transfer a pattern of the reticle on the resist film. Subsequently, a second sheet of the reticle is aligned to transfer a pattern of the reticle on the same resist film.
Then, a surface inspection, a pattern size inspection and inspection of reticle alignment are carried out. In the pattern size inspection, whether each reticle pattern is transferred on the resist film under suitable exposure conditions and focus conditions is ascertained. Also in the reticle alignment inspection, the amount of misalignment between patterns on the lower layer and/or on the same layer is measured so that alignment of all reticles to have been used is confirmed to be within a predetermined value.
Besides, a phase edge technology which is one of the multiple exposure process is currently attracting a great deal of attention. Mainly two sheets of reticles are used in the phase edge technology. One is a Levenson phase shift mask and the other is a binary mask or a half tone phase shift mask and the like. The Levenson phase shift mask is processed in a manner that the phase of transmission light is shifted by π (180°) sandwiching a region to form gate electrodes. A pattern in which only the gate electrodes are narrowed can be formed by using these two sheets of reticles. The order of the exposure step in the phase edge technology is the same as that of the multiple exposure process described above. It should be noted that since design data for the Levenson phase shift mask used in the phase edge technology is designed to dispose a shifter pattern only on a portion to be a gate electrode, it is prepared based on the layout of the other sheet of reticles.
On the other hand, in the phase edge technology, since the shifter pattern is required to be designed based on a design data for an original gate electrode, in other words, a design data for the other reticle (exposure mask), it is a matter of course that regions capable of disposing shifters are required to exist on both sides of the original gate electrode. This is because when size of the shifter pattern is not equal to or more than a predetermined value, the contrast is lowered so that effect of the phase shift cannot be sufficiently obtained. However, due to recent rapid miniaturization of the device, it becomes difficult to secure a region of sufficient width.
Especially, a portion having a great influence due to being incapable of securing the region for the shifter pattern is wiring formed in the same layer as the layer having the gate electrode therein. Since width between the gate electrode and the wiring is narrowed as the miniaturization advances, when shifter patterns with a sufficient width are intended to secure on both sides of the gate electrode pattern in the reticle, a width between the shifter pattern and the wiring pattern becomes remarkably narrow, and sometimes they are adjacent to each other.
Accordingly, when to exposure using this shifter pattern, a result of subsequent development shows that the wiring pattern transferred on a resist film sometimes retracts further more than the design data. Further when two gate electrodes are disposed sandwiching wiring therebetween, the wiring may break down sometimes. Therefore, it is quite difficult to use a shifter pattern having enough width.
Hence, a method of manufacturing a semiconductor device which can solve the above-described disadvantage is disclosed in Japanese Patent Application Laid-open No. 2000-227652. In the method disclosed in this publication, first, a hard mask is formed on a layer to be patterned. Then, a first resist film is formed on the hard mask. Next, a pattern of a first reticle is transferred on the first resist film. After that, the hard mask is etched using the first resist film as a mask. Thereafter, a second resist film is formed on this hard mask to transfer a pattern of a second reticle on the second resist film. Subsequently, the hard mask is etched again using the second resist film as a mask. Then, patterning of a layer to be patterned is carried out using this hard mask. According to this method, it is possible to avoid breaking down of wired portion.
However, as the recent miniaturization of patterns and pitches advances, it sometimes happens that a pattern with a desired size cannot be formed when the phase edge technology is used alone. In such a case, a trimming technology has been sometimes used together with the phase edge technology, but it still has a disadvantage that width of the wiring becomes narrower than the design value due to adoption of the trimming technology. Incidentally, the trimming technology is a technology to make an organic resin film such as a resist film and the like narrower by etching.
In general, wiring is required to be low in resistance. This requirement is necessary to avoid disadvantages in such that propagation velocity of a signal is reduced when the resistance is high. Therefore, a method of reducing the resistance by changing the wiring surface into silicide with Co, Ti, or the like is adopted. However, even when the resistance of the wiring is reduced by such a method, it becomes impossible to obtain the predetermined characteristics if the wiring gets narrower than the design value, especially when the wiring is long. As a result, even when the operational speed of a transistor is increased through shortening of the gate length, performance of the semiconductor device cannot be improved sufficiently because of deterioration of the performance caused by the wiring. Such a disadvantage has not been solved even with the method disclosed in the above-described publication.
Though it is possible to avoid merely lowering of the propagation speed of the signal by simply making the wiring pattern intentionally broader at the step of designing, it is quite difficult in a semiconductor device in which miniaturization of pitches is going on to design only the wiring broader than a predetermined value in advance. In other words, when forming a resist pattern, since only the wiring pattern gets broader without changing the pitches thereof, the width between the patterns gets much narrower. As a result, adjacent patterns transferred on the resist film may connect to each other. Besides, broadening of the wiring is against the requirement of miniaturization of pitches.
As described above, conventionally, formation of a fine gate electrode using the phase edge technology together with the trimming technology has been extremely difficult.